1. Field of the Invention
The present invention relates to an analog-to-digital (AD) conversion circuit and an imaging apparatus having the same.
Priority is claimed on Japanese Patent Application No. 2011-256143, filed Nov. 24, 2011, the content of which is incorporated herein by reference.
2. Description of Related Art
In FIG. 25, part of a configuration of a time-to-digital converter (TDC) type AD conversion circuit in accordance with the related art is selectively illustrated. Hereinafter, the TDC type AD conversion circuit is simply referred to as an AD conversion circuit. The circuit illustrated in FIG. 25 includes a voltage-controlled oscillator (VCO) 1100, a latch unit 1108, a binarization unit 1106, and a count unit 1101. The VCO 1100 has an oscillation circuit in which nine delay units (not AND (NAND) circuits NAND0 to NAND8) are connected. The latch unit 1108 holds output signals CK0 to CK8 (lower-order phase signals) of the VCO 1100. The binarization unit 1106 binarizes data of the latch unit 1108 (equivalent to states of the output signals CK0 to CK8 of the VCO 1100). The count unit 1101 has a counter circuit that performs a count operation using the output signal CK8 of the NAND circuit NAND8 as a count clock.
A start pulse StartP is input to one input terminal of the NAND circuit NAND0 constituting the VCO 1100. The output signal CK8 of the NAND circuit NAND8 is input to the other input terminal of the NAND circuit NAND0. A power supply voltage VDD is input to one input terminal of each of the NAND circuits NAND1 to NAND7. Output signals of previous-stage NAND circuits are input to the other input terminals of the NAND circuits NAND1 to NAND7. During an operation period of the AD conversion circuit, the power supply voltage VDD is set to a high level. The output signal CK5 of the NAND circuit NAND5 is input to one input terminal of the NAND circuit NAND8. The output signal CK7 of the previous-stage NAND circuit NAND7 is input to the other input terminal of the NAND circuit NAND8. The output signal CK5 of the NAND circuit NAND5 is input to the NAND circuit NAND8 of a third subsequent stage in addition to the NAND circuit NAND6 of a first subsequent stage. Thereby, a feed-forward loop is formed and a so-called “asymmetric oscillation circuit” is configured.
Next, an operation of the AD conversion circuit will be described. In FIG. 26, waveforms of the start pulse StartP and the output signals CK0 to CK8 of the VCO 1100 are illustrated. First, a logic state of the start pulse StartP changes from an L (=Low) state to an H (=High) state, and hence the VCO 1100 starts a transition operation. In this transition operation, logic states of signals output by the NAND circuits constituting the VCO 1100 sequentially change. The count unit 1101 starts the count operation simultaneously when the VCO 1100 starts the transition operation. A reference signal generation unit (not illustrated) starts the generation of a ramp wave (reference signal). The ramp wave generated by the reference signal generation unit is a signal having a level that changes (increases or decreases) in one direction with the passage of time.
An analog signal serving as an AD conversion target and a ramp wave variant approximately in synchronization with operations of the VCO 1100 and the count unit 1101 are input to a comparison unit (not illustrated). In parallel with this, the output signals CK0 to CK8 of the VCO 1100 are input to the latch unit 1108, and the output signal CK8 of the VCO 1100 is input to the count unit 1101. If a magnitude relationship of two input signals input to the comparison unit is switched, an output signal CO of the comparison unit is inverted. At this time, the latch unit 1108 holds (latches) the logic states of the output signals CK0 to CK8 of the VCO 1100, and the count unit 1101 holds a count value.
The output signals CK0 to CK8 of the VCO 1100 operate approximately in synchronization with the ramp wave input to the comparison unit. Thus, digital data corresponding to the analog signal serving as the AD conversion target is held in the latch unit 1108 and the count unit 1101. Thereafter, in the binarization unit 1106, data based on the logic state held by the latch unit 1108 is binarized, and digital data including the binary data (lower-order data) and data (higher-order data) based on the count value held by the count unit 1101 is output as the AD conversion result.
The states (combinations of the states of the output signals CK0 to CK8 of the VCO 1100) of lower-order phase signals (equivalent to the output signals CK0 to CK8 of the VCO 1100) latched in the latch unit 1108 become, for example, a total of eight states including states 0 to 7. Binarization is performed by encoding the output signals CK0 to CK8 of the VCO 1100 in the eight states. For example, when the count unit 1101 performs the count operation at a rising edge of the output signal CK8 of the VCO 1100, the combinations of the logic states of the output signals CK0 to CK8 become states 0 to 7 in eight equal periods into which a period (a period from the rising edge of the output signal CK8 to the next rising edge) in which the count unit 1101 performs one count operation is divided.
Next, a case in which the AD conversion circuit in accordance with the above-described related art is applied to a column analog-to-digital converter (ADC) type solid-state imaging apparatus (for example, Japanese Unexamined Patent Application, First Publication No. 2011-23887) is considered. The VCO 1100 is arranged outside a column unit corresponding to a pixel column. The comparison unit, the latch unit 1108, the binarization unit 1106, and the count unit 1101 are arranged inside the column unit. A pixel signal output from a pixel is input as the analog signal serving as the AD conversion target to the comparison unit. When the output signal CO of the comparison unit has been inverted, the lower-order phase signals, which are the output signals CK0 to CK8 of the VCO 1100, are latched in the latch unit 1108. After the lower-order phase signals latched in the latch unit 1108 have been binarized by the binarization unit 1106, the binary signals are output as digital data, which is the AD conversion result, along with the count value of the count unit 1101.
Hereinafter, content of a process of detecting a thermometer code and an encoding error will be described. FIG. 27 is a timing chart illustrating a binarization procedure in the AD conversion circuit including the circuit of FIG. 25. An example in which the count unit 1101 performs the count operation at the rising edge of the output signal CK8 of the VCO 1100 will be described.
In FIG. 27, the output signals of the VCO 1100 illustrated in FIG. 26 are arranged to be a group of signals that sequentially rise (change from the L state to the H state) at predetermined time intervals. Specifically, the output signals are arranged in the order of the output signals CK1, CK3, CK5, CK7, CK0, CK2, CK4, and CK6. As illustrated in FIG. 27, when a predetermined time (corresponding to a delay time for two NAND circuits) has elapsed after the output signal CK1 has changed from the L state to the H state, the output signal CK3 changes from the L state to the H state. When a predetermined time (corresponding to a delay time for two NAND circuits) has elapsed after the output signal CK3 has changed from being in the L state to being in the H state, the output signal CK5 changes from being in the L state to being in the H state. Thereafter, likewise, the output signals CK7, CK0, CK2, CK4, and CK6 sequentially change from being in the L state to being in the H state.
The lower-order phase signal is binarized, for example, using an output signal other than the output signal CK8. Specifically, the binarization is performed by performing the following <Procedure (1)> to <Procedure (7)> in time series.
In the procedures, a position at which the logic state changes from the H state to the L state, that is, the thermometer code, is detected in a signal group (signal stream) in which the output signals CK1, CK3, CK5, CK7, CK0, CK2, CK4, and CK6 latched in the latch unit 1108 have been arranged in this order, and the state is determined according to the detected thermometer code. The “change of the logic state from the H state to the L state” indicates that a previous output signal is in the H state and a subsequent output signal is in the L state when the output signals constituting the above-described signal group are sequentially viewed.
For example, in the case of state 7, if the logic states of the output signals CK1, CK3, CK5, CK7, CK0, CK2, CK4, and CK6 are viewed in this order, the logic state changes from the H state to the L state between the output signal CK4 and the output signal CK6. Even in the other states 0 to 6, the logic state between two output signals corresponding to each state changes from being in the H state to being in the L state. That is, it is possible to determine states by detecting positions at which the logic states of the output signals arranged as illustrated in FIG. 27 change.
Hereinafter, the procedures will be described.
<Procedure (1)> . . . Determination of whether or not the state is “state 7”
The logic states of the output signals CK6 and CK4 are compared. If there is a thermometer code here, the state is determined to be “state 7.”
<Procedure (2)> . . . Determination of whether or not the state is “state 6”
The logic states of the output signals CK4 and CK2 are compared. If there is a thermometer code here, the state is determined to be “state 6.”
<Procedure (3)> . . . Determination of whether or not the state is “state 5”
The logic states of the output signals CK2 and CK0 are compared. If there is a thermometer code here, the state is determined to be “state 5.”
<Procedure (4)> . . . Determination of whether or not the state is “state 4”
The logic states of the output signals CK0 and CK7 are compared. If there is a thermometer code here, the state is determined to be “state 4.”
<Procedure (5)> . . . Determination of whether or not the state is “state 3”
The logic states of the output signals CK7 and CK5 are compared. If there is a thermometer code here, the state is determined to be “state 3.”
<Procedure (6)> . . . Determination of whether or not the state is “state 2”
The logic states of the output signals CK5 and CK3 are compared. If there is a thermometer code here, the state is determined to be “state 2.”
<Procedure (7)> . . . Determination of whether or not the state is “state 1”
The logic states of the output signals CK3 and CK1 are compared. If there is a thermometer code here, the state is determined to be “state 1.”
When it is determined that the state is not any one of “state 7” to “state 1” in <Procedure (1)> to <Procedure (7)>, the state is “state 0.” Accordingly, it is not particularly necessary to determine whether or not the state is “state 0.”
However, there are timings at which falling edges of the output signals CK0 and CK7 among the output signals CK0 to CK8 of the asymmetric oscillation circuit (VCO 1100) are approximately simultaneous. For example, if the phase of the output signal CK0 has been slightly advanced or if the phase of the output signal CK7 has been slightly delayed even when the logic states of the output signals CK0 to CK8 correspond to “state 0,” there are cases in which the logic state of the output signal CK0 becomes the L state and the logic state of the output signal CK7 becomes the H state according to the timing at which the latch unit 1108 has latched the output signals CK0 to CK8. When the logic state of the output signal CK0 becomes the L state and the logic state of the output signal CK7 becomes the H state, the thermometer code is detected in the step of <Procedure (4)> if the above-described <Procedure (1)> to <Procedure (7)> are performed. Thereby, an encoding error in which it is erroneously determined that the state is “state 4” occurs.
Next, another example of the encoding error will be described. Hereinafter, description will be given using an example in which the count unit 1101 performs the count operation at the falling edge of the output signal CK8 of the VCO 1100. FIG. 28 illustrates the waveforms of the start pulse StartP and the output signals CK0 to CK8 of the VCO 1100. When the count unit 1101 performs the count operation at the falling edge of the output signal CK8 of the VCO 1100, the combinations of the logic states of the output signals CK0 to CK8 become states 0 to 7 in eight equal periods into which a period (a period from the falling edge of the output signal CK8 to the next falling edge) in which the count unit 1101 performs one count operation is divided as illustrated in FIG. 28.
FIG. 29 is a timing chart illustrating a binarization procedure in the AD conversion circuit including the circuit of FIG. 25. In FIG. 29, the output signals of the VCO 1100 illustrated in FIG. 28 are arranged to be a group of signals that sequentially fall (change from being in the H state to being in the L state) at predetermined time intervals. Specifically, the output signals are arranged in the order of the output signals CK1, CK3, CK5, CK0, CK2, CK4, CK6, and CK8. As illustrated in FIG. 29, when a predetermined time (corresponding to a delay time for two NAND circuits) has elapsed after the output signal CK1 has changed from being in the H state to being in the L state, the output signal CK3 changes from being in the H state to being in the L state. When a predetermined time (corresponding to a delay time for two NAND circuits) has elapsed after the output signal CK3 has changed from being in the H state to being in the L state, the output signal CK5 changes from being in the H state to being in the L state. Thereafter, likewise, the output signals CK0, CK2, CK4, CK6, and CK8 sequentially change from being in the H state to being in the L state.
The lower-order phase signal is binarized, for example, using an output signal other than the output signal CK7. Specifically, the binarization is performed by performing the following <Procedure (1)> to <Procedure (7)> in time series.
In the procedures, the state is determined according to a position at which the logic state changes from the L state to the H state in a signal group (signal stream) in which the output signals CK1, CK3, CK5, CK0, CK2, CK4, CK6, and CK8 latched in the latch unit 1108 have been arranged in this order. That is, the thermometer code is detected and the state is determined according to the detected thermometer code. The “change of the logic state from the L state to the H state” indicates that a previous output signal is in the L state and a subsequent output signal is in the H state when the output signals constituting the above-described signal group are sequentially viewed.
For example, in the case of state 7, if the logic states of the output signals CK1, CK3, CK5, CK0, CK2, CK4, CK6, and CK8 are viewed in this order, the logic state between the output signal CK6 and the output signal CK8 changes from being in the L state to being in the H state. Even in the other states 0 to 6, the logic state changes from the L state to the H state between two output signals corresponding to each state. That is, it is possible to determine states by detecting positions at which the logic states of the output signals arranged as illustrated in FIG. 29 change.
Hereinafter, the procedures will be described.
<Procedure (1)> . . . Determination of whether or not the state is “state 7”
The logic states of the output signals CK8 and CK6 are compared. If there is a thermometer code here, the state is determined to be “state 7.”
<Procedure (2)> . . . Determination of whether or not the state is “state 6”
The logic states of the output signals CK6 and CK4 are compared. If there is a thermometer code here, the state is determined to be “state 6.”
<Procedure (3)> . . . Determination of whether or not the state is “state 5”
The logic states of the output signals CK4 and CK2 are compared. If there is a thermometer code here, the state is determined to be “state 5.”
<Procedure (4)> . . . Determination of whether or not the state is “state 4”
The logic states of the output signals CK2 and CK0 are compared. If there is a thermometer code here, the state is determined to be “state 4.”
<Procedure (5)> . . . Determination of whether or not the state is “state 3”
The logic states of the output signals CK0 and CK5 are compared. If there is a thermometer code here, the state is determined to be “state 3.”
<Procedure (6)> . . . Determination of whether or not the state is “state 2”
The logic states of the output signals CK5 and CK3 are compared. If there is a thermometer code here, the state is determined to be “state 2.”
<Procedure (7)> . . . Determination of whether or not the state is “state 1”
The logic states of the output signals CK3 and CK1 are compared. If there is a thermometer code here, the state is determined to be “state 1.”
When it is determined that the state is not any one of “state 7” to “state 1” in <Procedure (1)> to <Procedure (7)>, the state is “state 0.” Accordingly, it is not particularly necessary to determine whether or not the state is “state 0.”
However, there are timings at which falling edges of the output signals CK8 and CK6 among the output signals CK0 to CK8 of the asymmetric oscillation circuit (VCO 1100) are approximately simultaneous. For example, if the phase of the output signal CK8 has been slightly advanced or if the phase of the output signal CK6 has been slightly delayed even when the logic states of the output signals CK0 to CK8 correspond to “state 3,” there are cases in which the logic state of the output signal CK6 becomes the L state and the logic state of the output signal CK8 becomes the H state according to the timing at which the latch unit 1108 has latched the output signals CK0 to CK8. When the logic state of the output signal CK6 becomes the L state and the logic state of the output signal CK8 becomes the H state, the thermometer code is detected in the step of <Procedure (1)> if the above-described <Procedure (1)> to <Procedure (7)> are performed. Thereby, an encoding error in which it is erroneously determined that the state is “state 7” occurs.